A typical semiconductor memory, shown in FIG. 1, includes a matrix of memory cells 11 arranged in rows and columns. Each memory cell 11 may be a single, variable threshold, floating gate device, such as an EPROM or EEPROM device, with its source and drain terminals connected between a column line 13 and ground and with its control gate connected to a row line 15. Row select signals X1, X2, etc. are applied to respective row lines 15 in order to apply an active voltage level to the control gates of, and thereby enable, a selected row of memory cells 11. Pass transistors 17 are connected at the end of each column line 13. Column select signals Y1, Y2, etc. are applied to respective gates of pass transistors 17 in order to enable a pass transistor 17 in a selected column, and thereby connect the selected column line 13 and associated memory cells 11 to a sense amplifier 19 via a conductive line 21. A sense amplifier 19 typically includes a first circuit portion 23 for sensing a small amount of current i on the conductive line 21 and producing a voltage level on an output 25 of the current sensing circuit portion 23 of sense amplifier 19 corresponding to the amount of current i that is sensed. Sense amplifier 19 typically also includes a second circuit portion 27 connected to the output 25 of the current sensing circuit portion 23 for producing a first voltage level on output line 29 whenever the voltage level on line 25 drops below a threshold voltage (i.e., when the current i exceeds a threshold current) and producing a second voltage level on output line 29 whenever the voltage level on line 25 is above the threshold voltage (i.e., when the current i is less than the threshold current). For example, a CMOS inverter with an unbalanced threshold (e.g., an inverter with a significantly wider n-channel transistor) could be used for the amplifying circuit portion 27 of the sense amplifier 19. An additional inverter could be included to reinvert the output.
The operation of the memory circuit in FIG. 1 consists of successive selections by the row and column select signals X1, X2, etc., Y1, Y2, etc., of individual memory cells 11 in the specified row and column locations containing stored bits of information to be retrieved. Memory cells 11 that are not selected are nonconductive and effectively act as capacitors between the column lines 13 and ground. A memory cell 11 which is selected will be either conductive or nonconductive, depending on whether or not a charge has been stored by previous programming in the floating gate of the EPROM or EEPROM device that comprises that memory cell 11. Storing or erasing a charge in the floating gate alters the thresh-old voltage of the device, thereby determining whether the device will turn on or remain off when a bias voltage is applied by the corresponding row select signal X1, X2, etc. to the device's control gate.
Ideally, the only contribution to the current i on conductive line 21 leading to the sense amplifier 19 will be the cell current i.sub.cell through the selected memory cell 11. This situation is represented by the curve 31 in FIG. 2a, in which the current i rises to a steady state level i.sub.0 when the memory cell selected at time t.sub.0 begins to turn on and conduct current. The resulting output voltage generated by the sense amplifier 19 on output line 29 is represented by the curve 32 in FIG. 2a. Prior to the time t.sub.O, when another, nonconductive, memory cell with no cell current (i=0) is being sensed, the output voltage is at a first voltage level V.sub.1. Subsequent to the time t.sub.0 when the newly selected memory cell has begun to conduct, the output voltage will begin to fall, once the current i on conductive line 21 exceeds a threshold current level. Provided the current i remains greater than the threshold current level, the output voltage will continue to fall until it reaches a second voltage level V.sub.2. The effect of other transitions from one selected memory cell to another, such as from a non-conductive cell to another nonconductive cell, from a conductive cell to a nonconductive cell, and from one conductive cell to another conductive cell, upon the resulting output voltage provided by the sense amplifiers will be readily recognized by comparison with the case shown in FIG. 2a. Further, it will also be recognized that the polarity of the output could be reversed so that the second voltage level V.sub.2 is greater than the first voltage level V.sub.1.
The ideal situation, in which cell current i.sub.cell is the only significant contribution to the current i on conductive line 21, frequently does not apply. There is generally a large cell capacitance (3 to 4 pF) from the column of memory cells 11 connected to a column line 13. In contrast, there is a relatively small capacitance (0.2 to 0.3 pF) from the wiring of the structure, i.e., from the conductive lines themselves. Whenever there is a change in the selected column, as soon as the pass transistor 17 at the end of the selected column turns on, a charging current i.sub.charge will flow through the conductive line 21 and selected column line 13 in order to charge up the column line 13. This charging current i.sub.charge is present because the small capacitance from the wiring is only 5-10% of the cell capacitance and thus unable by itself to completely charge up the column line 13 with all of its memory cells 11. The sense amplifier 19 sees this momentary charging current i.sub.charge, in addition to any cell current i.sub.cell from the selected memory cell 11, and will thus produce a corresponding glitch in the voltage output. This situation is illustrated in FIGS. 2b and 2c showing the current i and voltage output for the cases where the previously selected memory cell in one column is nonconductive and the newly selected memory cell in another column is, respectively, nonconductive (FIG. 2b) and conductive (FIG. 2c) when selected.
In FIG. 2b, the charging current i.sub.charge is the only significant contribution to the current i, represented by curve 33, on conductive line 21. Ideally, the voltage output from the sense amplifier 19, represented by curve 34, would remain at first voltage level V.sub.1, since both the previously selected and newly selected memory cells are programmed to be nonconductive (i.sub.cell =0). However, the large charging current that occurs immediately after time t.sub.0 when the memory cell selection is switched exceeds the current threshold for the sense amplifier 19, causing the sense amplifier output to change to the second voltage level V.sub.2. Once the charging current diminishes and drops below the current threshold level at time t.sub.1, the sense amplifier output voltage returns to the first voltage level V.sub.1. In FIG. 2c, both the cell current i.sub.cell and the charging current i.sub.charge contribute to the current i, represented by curve 35, on conductive line 21 sensed by the sense amplifier 19. That is, i=i.sub.cell +i.sub.charge. Ideally, the voltage output from the sense amplifier 19, represented by curve 36, would be identical to curve 32 in FIG. 2a. The voltage would change from level V.sub.1 to level V.sub.2 and remain there, at least until the next memory cell selection. However, when the charging current diminishes to zero at time t.sub.1, the cell current i.sub.cell may not yet have reached the threshold current for the sense amplifier 19. A momentary spike 37 is produced in the voltage output until the threshold current is reached.
The glitches in the output voltage caused by the charging current are sufficiently large that they can easily be misinterpreted as data when the output is sent to other circuits in the system, rather than as the noise that they actually are. Further, in some types of sense amplifiers, the noise from these glitches can feed back into the sense amplifier and cause it to oscillate, thereby further increasing noise in the system.
In U.S. Pat. No. 5,056,064 Iwahashi et al. describe a semiconductor memory integrated circuit having a memory cell array with rows and columns of memory cells for storing data, address input terminals for receiving externally supplied row and column address input signals from circuits outside the memory circuit, row and column address buffers and decoders for selectively driving row lines and column selection lines in response to the address input signals received by the address input terminals, a column gate circuit for selecting a bit line to which memory cells in the memory cell array are respectively connected on the basis of a signal from the column selection lines, and a sense amplifier for detecting data stored in a memory cell on the selected bit line and driven by the selected row line corresponding to the address input signals. The memory circuit also includes a transfer control circuit connected between the sense amplifier and an output buffer circuit for receiving the detected data from the sense amplifier and controlling the transfer of this data to the output buffer circuit. Operation of the transfer control circuit is controlled by output pulse signals from a pulse signal generator. The pulse signal generator detects logic level changes of the address input signals from the address input terminals and outputs a pulse signal whenever there is a change in at least one of the address input signals. The transfer control circuit has a faster response time for quickly transferring detected data to the output buffer when the pulse signal is generated, and a slower response time for delaying transfer of signals while the pulse signal is not present in order to prevent the outputting of erroneous signals due to power source voltage variations.
An object of the invention is to provide a data retrieval circuit for a high speed semiconductor memory integrated circuit that reduces the noise in the data signal output from the memory that is seen by the rest of the system employing such memory circuits.